doi: 10.7763/IJET.2012.V4.482
Design and Development of 8-Bits Fast Multiplier for Low Power Applications
Vasudev G
1
,
Rajendra Hegadi
2
- 1 the ACS College of Engineering, Bangalore, India- 560 032
- 2 the Pragati College of Engineering and Management, Raipur (C.G)-492015, India
Abstract
High speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very high speed supporting higher data rates. In DSP applications, multiplication is one of the most utilized arithmetic operations as part of filters, convolves and transforms processors. Improving multipliers design directly benefits the high performance embedded processors used in consumer and industrial electronic products. Hence there is a need for design and development of high-speed architectures for N-bit multipliers supporting high speed and power. Here we review the architecture reported in the literature for multipliers and critical issues degrading the speed and power of these multiplier. Based on this review suitable modifications are suggested in the design for high speed and low power multipliers.
Keywords
- CPA
- DSP
- microprocessor
- multiplier
How to Cite
Vasudev G and Rajendra Hegadi, "Design and Development of 8-Bits Fast Multiplier for Low Power Applications," International Journal of Engineering and Technology, vol. 4, no. 6, pp. 774-780, 2012. https://doi.org/ 10.7763/IJET.2012.V4.482
Copyright & License
Copyright © 2012 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).