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Editor-in-chief
Prof. T. Hikmet Karakoc
Anadolu University, Faculty of Aeronautics and Astronautics, Turkey

IJET 2011 Vol.3(3): 274-278 ISSN: 1793-8236
DOI: 10.7763/IJET.2011.V3.237

Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity

Rakesh Kumar Saxena, Neelam Sharma and A. K. Wadhwani

Abstract—Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits which are designed to perform high-speed arithmetic operations. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was modified by Neelam Sharma in 2006 using universal logic. The proposed adder is re-modified for reducing the number of gates and thus the circuit complexity and cost. Further due to the reduced gate count, circuit area, number of levels and hence implementation time is reduced up to 1% as proved by VHDL synthesis report. Since multiplication is repetitive addition, the implementation time of the multiplier circuit will be reduced to a great extent. Thus the proposed RBSD adder cell using NOR and NAND gates will be a boost in the speed of sophisticated ALU Design of high speed machines.

Index Terms—Carry free addition, fast Multiplier, Fast Computing, High-speed arithmetic, RBSD.

Rakesh Kumar Saxena is Associate Professor in the Institute of Engg. &Technology, Alwar, Rajasthan, India (e-mail: saxenark06@gmail.com).
Neelam Sharma is Professor of Electronics Engineering and Principal of the Institute of Engg. & Technology, Alwar, Rajasthan, India (e-mail: neelam_sr@yahoo.com).
A. K. Wadhwani is the Professor of the Electrical Engineering in Madhav Institute of Technology & Science, Gwalior, M. P., and India. (e-mail:wadhwani_arun@rediffmail.com)

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Cite: Rakesh Kumar Saxena, Neelam Sharma and A. K. Wadhwani, "Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity," International Journal of Engineering and Technology vol. 3, no. 3, pp. 274-278, 2011.

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