Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design - Volume 3 Number 3 (Jun. 2011) - IJET
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General Information
Editor-in-chief
Prof. T. Hikmet Karakoc
Anadolu University, Faculty of Aeronautics and Astronautics, Turkey

IJET 2011 Vol.3(3):279-286 ISSN: 1793-8236
DOI: 10.7763/IJET.2011.V3.238

Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design

Ahmed Sayed and Hussain Al-Asaad

Abstract—Synchronous logic design is the dominant main stream integrated circuit design methodology. Flip-flops are an inherent building block in any synchronous design. Furthermore flip-flops constitute most of the load on the clock distribution and power networks, which are the main power consuming networks of a synchronous integrated circuit. We survey, design and simulate a superset of flip-flops designed for low power and high performance. We highlight the basic design features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics. Moreover, we propose a new flip-flop design. We go in depth into a finer granularity comparison of the lowest peak power surveyed flip-flops reported in the literature; we show the competitiveness of the new design and make our recommendations.

Index Terms—Flip-flop design, Low-Power circuits, Power and delay estimation, VLSI circuits.

[PDF]

Cite: Ahmed Sayed and Hussain Al-Asaad, "Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design," International Journal of Engineering and Technology vol. 3, no. 3, pp. 279-286, 2011.

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