doi: 10.7763/IJET.2011.V3.237
Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity
Rakesh Kumar Saxena
1
,
Neelam Sharma
1
,
A. K. Wadhwani
2
- 1 Institute of Engg. &Technology, Alwar, Rajasthan, India
- 2 Institute of Technology & Science, Gwalior, M. P., and India
Abstract
Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits which are designed to perform high-speed arithmetic operations. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was modified by Neelam Sharma in 2006 using universal logic. The proposed adder is re-modified for reducing the number of gates and thus the circuit complexity and cost. Further due to the reduced gate count, circuit area, number of levels and hence implementation time is reduced up to 1% as proved by VHDL synthesis report. Since multiplication is repetitive addition, the implementation time of the multiplier circuit will be reduced to a great extent. Thus the proposed RBSD adder cell using NOR and NAND gates will be a boost in the speed of sophisticated ALU Design of high speed machines.
Keywords
- Carry free addition
- fast Multiplier
- Fast Computing
- High-speed arithmetic
- RBSD
How to Cite
Rakesh Kumar Saxena, Neelam Sharma, and A. K. Wadhwani, "Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity," International Journal of Engineering and Technology, vol. 3, no. 3, pp. 274-278, 2011. https://doi.org/ 10.7763/IJET.2011.V3.237
Copyright & License
Copyright © 2011 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).