doi: 10.7763/IJET.2012.V4.386
A 6-bit 2GS/s Low Power Flash ADC
,
Zhi-Ming Lin
2
- 1 the Graduate Program of Integrated Circuit Design of Computer Science and Information Engineering, National Changhua University of Education
- 2 the Department of Computer Science and Information Engineering, National Changhua University of Education
Abstract
In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.
Keywords
- Analog-to-digital converter
- comparator
- flash
- inverter
How to Cite
Jyun-Syong Lai and Zhi-Ming Lin, "A 6-bit 2GS/s Low Power Flash ADC," International Journal of Engineering and Technology, vol. 4, no. 4, pp. 369-371, 2012. https://doi.org/ 10.7763/IJET.2012.V4.386
Copyright & License
Copyright © 2012 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).