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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • Executive Editor: Ms. Jennifer Zeng
    • Abstracting/ Indexing: Inspec (IET), CNKI Google Scholar, EBSCO, ProQuest, Crossref, etc.
    • E-mail: ijet@vip.163.com
Editor-in-chief
IJET 2011 Vol.3(4): 431-434 ISSN: 1793-8236
DOI: 10.7763/IJET.2011.V3.265

Sine/Cosine Generator Using Pipelined CORDIC Processor

R. Ranga Teja and P. Sudhakara Reddy

Abstract—At present, many of the computations in signal processing and wireless communication applications are linked with complex analysis of several functions. These complex functions are combination of sine and cosine terms that generally spread in the channel. Most of these functions can be split into elementary functions. In this paper we present a hardware efficient architecture by using CORDIC algorithm for the calculation of sine and cosine functions. This approach is simulated using ModelSim simulation software, synthesized using Xilinx ISE design suite and the proposed architecture is implemented on Xilinx FPGA target device i.e. SPARTAN 3E. Finally, the device utilization summary and timing reports are presented.

Index Terms—CORDIC, FPGA, Pipelined processor, sine and cosine generator.

R. Ranga Teja, Student, Dept. of ECE, Srikalahasteeswara Institute of Technology, Srikalahasthi, Andhra Pradesh,  India. Ph:09985259705,E-mail:rangateja@gmail.com.
P. Sudhakara Reddy, Associate Professor, Dept. of ECE, Srikalahasteeswara Institute of Technology, Srikalahasthi, Andhra Pradesh, India. Ph: 09703415601, E-mail:psr_vlsi_dsp@rediffmail.com.

[PDF]

Cite: R. Ranga Teja and P. Sudhakara Reddy "Sine/Cosine Generator Using Pipelined CORDIC Processor," International Journal of Engineering and Technology vol. 3, no. 4, pp. 431-434, 2011.

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