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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • Managing Editor: Ms. Jennifer Zeng
    • Abstracting/ Indexing: Inspec (IET), CNKI Google Scholar, EBSCO, ProQuest, Crossref, etc.
    • E-mail: ijet_Editor@126.com
IJET 2011 Vol.3(3): 230-234 ISSN: 1793-8236
DOI: 10.7763/IJET.2011.V3.229

Design of Optimized Reversible BCD Adder/Subtractor

Rashmi S. B, Praveen B, and Tilak B G.

Abstract—Reversible logic has emerged as one of the most important research area in the past few decades. Reversible or information lossless circuits have applications in nanotechnology, digital signal processing, communication, computer graphics and cryptography. It is also a fundamental requirement in the emerging field of quantum computing. In this paper an optimized method is proposed to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. In order to optimize the design, nines compliment gate (NCG) and BSCL gates are proposed. This proposed reversible BCD adder/subtractor is evaluated and optimized in terms of gate count, constant inputs and garbage outputs.

Index Terms—Basic reversible gates; Reversible BCD adder; Reversible BCD subtractor; Constant input; Garbage; Gate count; Optimization.

The authors are with Department of Electronics and Communication, Sri Bhagawan Mahaveer Jain College of Engineering (SBMJCE, JU), Ramanagara, India (E-mail: rashmi_akshay@yahoo.co.in,praveen.prvs@yahoo.co.in, tilakbg90@yahoo.co.in).


Cite: Rashmi S. B, Praveen B, and Tilak B G., "Design of Optimized Reversible BCD Adder/Subtractor," International Journal of Engineering and Technology vol. 3, no. 3, pp. 230-234, 2011.

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