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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • Managing Editor: Ms. Jennifer Zeng
    • Abstracting/ Indexing: Inspec (IET), CNKI,  Google Scholar, EBSCO, ProQuest, Crossref, etc.
    • E-mail: ijet_Editor@126.com
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HOME > Archive > 2024 > Volume 16 Number 1 (2024) >
IJET 2024 Vol.16(1): 32-38
DOI: 10.7763/IJET.2024.V16.1251

HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration

Nuocheng Wang
Northeastern University, Boston, USA
Email: jw411711848@gmail.com

Manuscript received August 18, 2023; revised September 25, 2023; accepted November 3, 2023; published March 15, 2024

Abstract—This paper introduces the logic control flow of Field-Programmable Gate Array (FPGA). The process from analyzing a digital circuit description to component mapping on FPGA is described thoroughly. This transforming process is partitioned into three major stages: combinational logic synthesis, sequential logic inference, and technology mapping. Specific algorithms are discussed for each stage.

Keywords—Hardware Description Language (HDL), mapping, algorithm, Field-Programmable Gate Array (FPGA), configuration

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Cite: Nuocheng Wang, "HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration," International Journal of Engineering and Technology vol. 16, no. 1, pp. 32-38, 2024.

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