doi: 10.7763/IJET.2024.V16.1251
HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration
Nuocheng Wang
- Northeastern University, Boston, USA
- Manuscript received August 18, 2023
- revised September 25, 2023
- accepted November 3, 2023
- published March 15, 2024
Abstract
This paper introduces the logic control flow of Field-Programmable Gate Array (FPGA). The process from analyzing a digital circuit description to component mapping on FPGA is described thoroughly. This transforming process is partitioned into three major stages: combinational logic synthesis, sequential logic inference, and technology mapping. Specific algorithms are discussed for each stage.
Keywords
- Hardware Description Language (HDL)
- mapping
- algorithm
- Field-Programmable Gate Array (FPGA)
- configuration
How to Cite
Nuocheng Wang, "HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration," International Journal of Engineering and Technology, vol. 16, no. 1, pp. 32-38, 2024. https://doi.org/ 10.7763/IJET.2024.V16.1251
Copyright & License
Copyright © 2024 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).