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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • Managing Editor: Ms. Jennifer Zeng
    • Abstracting/ Indexing: Inspec (IET), CNKI Google Scholar, EBSCO, ProQuest, Crossref, Ulrich Periodicals Directory, Chemical Abstracts Services (CAS), etc.
    • E-mail: ijet_Editor@126.com
Editor-in-chief
IJET 2009 Vol.1(3): 208-212 ISSN: 1793-8236
DOI: 10.7763/IJET.2009.V1.39

FPGA Implementation of Multilevel Space Vector PWM Algorithms

Prawin Angel Michael and N. Devarajan

Abstract—Multilevel converters can meet the increasing demand of power rating and power quality associated with reduced harmonic distortion and lower electromagnetic interface.  With the increase in number of levels, it is necessary to control more and more switches in parallel. Field programmable gate arrays (FPGAs), with their concurrent processing capability, are suitable for the implementation of multilevel modulation algorithms. Among them, space vector pulse width modulation algorithms offer great flexibility to optimise switching waveforms. In this paper the SVPWM technique is analysed and implemented in FPGA. The SVPWM pulses thus generated through the FPGA tool is given as switching pulses to the VSI circuit to trigger the three phase induction motor. FPGA is chosen due to its fast prototyping, simple hardware and software design. Simulation results are provided along with the theoretical analysis in terms of THD, output fundamental voltage and voltage transfer ratio to verify the feasibility of operation.

Index Terms—Field programmable gate array (FPGA), voltage source inverter (VSI), space vector pulse width modulation (SVPWM), Printed circuit board (PCB).

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Cite: Prawin Angel Michael and N. Devarajan, "FPGA Implementation of Multilevel Space Vector PWM Algorithms," International Journal of Engineering and Technology vol. 1, no. 3, pp. 208-212, 2009.

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