Abstract—Switching loss has to be reduced in order to improve converter’s performance and efficiency. In high switching frequency, the effect of the loss is much greater. The duty ratio, dead time and inductor value are the limiting parameters which bring implications on the switching loss and hence total gate drive loss. Using PSpice circuit simulator, the optimization of these parameters have been carried out and it is found that the duty ratio, dead time and resonant inductor value are 20 %, 15 ns and 9 nH respectively. The details for choosing these values are presented in this paper.
Index Terms—PSpice simulation; resonant gate drive; switching loss
N. Z. Yahaya is with Universiti Teknologi PETRONAS, Malaysia. Currently, he is pursuing PhD in the field of power electronics. He can be contacted at tel: +605-3687823; fax: +605-3657443 (Email: norzaihar_yahaya@petronas.com.my)
K. M. Begam is a lecturer specializing in Physics and currently attached with Universiti Teknologi PETRONAS, Malaysia (Email: mumtajbegam@petronas.com.my)
M. Awan is with Electrical Engineering Department, Universiti Teknologi PETRONAS, Malaysia. His research interest is in the area of analog IC circuit design. (Email: mohdawan@petronas.com.my)
Cite: N. Z. Yahaya, K. M. Begam, and M. Awan, "The Analysis of Parameter Limitation in Diode-Clamped Resonant Gate Drive Circuit," International Journal of Engineering and Technology vol. 2, no. 1, pp. 17-22, 2010.
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