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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • APC: 500 USD
    • Managing Editor: Ms. Jennifer Zeng
    • Abstracting/ Indexing: Inspec (IET), CNKI Google Scholar, EBSCO, ProQuest, Crossref, Ulrich Periodicals Directory, Chemical Abstracts Services (CAS), etc.
    • E-mail: ijet_Editor@126.com
IJET 2012 Vol.4(5): 522-526 ISSN: 1793-8236
DOI: 10.7763/IJET.2012.V4.424

Implementation of FPGA Based Fault Injection Tool (FITO) for Testing Fault Tolerant Designs

Swathi Rudrakshi, Vasujadevi Midasala, and S. Naga Kishore Bhavanam

Abstract—Fault injection is mainly used to test and evaluate the fault-tolerance based designs. In current VLSI technology fault injection has become a popular technique for experimentally verifying the fault tolerant based designs. There are fundamentally two types of fault injection methods; they are hardware-based fault injection and software-based fault injection. Both have their own limitations and advantages. The FPGA synthesizable fault injection model can give reasonable solution with high speed testing platform and also allows good controllability and observability. Even though a considerable progress has been made in research part of the fault injection algorithms, there is a little progress done in developing a tool for FPGA based fault emulation. In this paper an FPGA-based fault injection tool (FITO) that supports several synthesizable fault models of digital systems are implemented using VHDL. Aim is to build real time fault injection mechanism with good controllability and observability. Fault injection will be done by applying some extra gates and wires to the original design description and modifying the target VHDL model of the target system. The design will be validated with state machine based example and applying different types of faults. Analysis will be carried out studying the controllability and observability of the proposed scheme. Comparison will be carried out to estimate the speed wise improvement with respect to software simulation based fault injection method. Modelsim Xilinx Edition (MXE) will be used for functional simulation and Xilinx ISE tools will be used for synthesis and performance analysis. Spartan-3E FPGA board will be used for on chip verification of the results with Chipscope software running on PC

Index Terms—VLSI, FITO, VHDL, fault modeling, modelsim, xilinx, GUI, spartan 3E FPGA kit.

S. Rudrakshi and S. N. K. Bhavanam are with the M. Tech. (VLSI-SD), Dept. of E.C. E. ATRI, JNTUH, Hyderabad, A.P, India (email: rudrakshiswathi@gmail.com, satyabhavanam@gmail.com).
V. Midasala is with the M. Tech. (VLSI-SD), Dept. of E.C.E BSIT, JNTUH Hyderabad, A.P, India (email: vasujadevi@gmail.com).


Cite: Swathi Rudrakshi, Vasujadevi Midasala, and S. Naga Kishore Bhavanam, "Implementation of FPGA Based Fault Injection Tool (FITO) for Testing Fault Tolerant Designs," International Journal of Engineering and Technology vol. 4, no. 5, pp. 522-526, 2012.

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