doi: 10.7763/IJET.2010.V2.130
A Shannon Based Low Power Adder Cell for Neural Network Training
- Electronics and Communication Engineering, Bannari Amman Institute of Technology, India
Abstract
The proposed full adders for low power and high performance neural network training circuits has been implemented using Shannon decomposition based technique for sum and carry operation. The hardware includes multiplier circuit for product term and an adder circuit to perform summation. The proposed full adder is designed using tanner EDA tools and the resulting parameters such as 25.6% improvement in power dissipation and 20% improvement in transistor count from the simulated output when compared with MC IT based adder cell.
Keywords
- MCIT
- Shannon adder cell
- power
- area
- propagation delay
How to Cite
K. Nehru, A. Shanmugam, S. Deepa, and R. Priyadarshini, "A Shannon Based Low Power Adder Cell for Neural Network Training," International Journal of Engineering and Technology, vol. 2, no. 3, pp. 258-262, 2010. https://doi.org/ 10.7763/IJET.2010.V2.130
Copyright & License
Copyright © 2010 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).