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General Information
    • ISSN: 1793-8236 (Online)
    • Abbreviated Title Int. J. Eng. Technol.
    • Frequency:  Quarterly 
    • DOI: 10.7763/IJET
    • APC: 500 USD
    • Managing Editor: Ms. Isa Yuan 
    • Abstracting/ Indexing:  CNKI,  Google Scholar, Crossref, EBSCO  etc.
    • E-mail: ijet_Editor@126.com
IJET 2017 Vol.9(1): 67-70
doi: 10.7763/IJET.2017.V9.947

Design of Addition/Subtraction for BIN/BCD Numbers

Tara Tavakoli , Nastaran Parvin , Safiyeh Nikkhahsani , Seyed Reza Talebiyan

  • Imamreza internationaluniversity, Mashhad, Iran

Abstract

This paper aims to find a solution for a new design of binary / BCD adder / subtraction to increase the speed of operations and decrease the delays in signed numbers as well as the unsigned ones. A very important operation in mathematics for digital systems is adding binary/BCD numbers. Many different ways have been presented for addition and subtraction of BCD,this paper has presents no signbit numbers adder and subtractor many papers presented adder and subtractor for binary BCD numbers but all of them have some problems with their final assessment in this paper this problem is solved by adding EOP (end of operation signal).Here, a new design for addition or subtraction has been offered, without taking the signbit in BCD format that works perfectly.

Keywords

  • Adder
  • subtractor
  • signbit
  • condition
  • Restructuring
  • EOP (end of operation signal)
947-CT306

How to Cite

Copied

Tara Tavakoli, Nastaran Parvin, Safiyeh Nikkhahsani, and Seyed Reza Talebiyan, "Design of Addition/Subtraction for BIN/BCD Numbers," International Journal of Engineering and Technology, vol. 9, no. 1, pp. 67-70, 2017. https://doi.org/ 10.7763/IJET.2017.V9.947

Copyright & License

Copyright © 2017 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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