Abstract—In the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell. This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.
Index Terms—On-Chip Integration, Sub-threshold Leakage, Static Noise Margin (SNM), Data Stability.
Shilpi Birla is with SPSU and PhD scholar at UK Tech University .
R.K.Singh is with UK Tech University and Manisha Pattanik is with ABV-IIITM Gwalior.
Cite: Shilpi Birla, R. K. Singh,and Manisha Pattnaik, "Static Noise Margin Analysis of Various Sram Topologies," International Journal of Engineering and Technology vol. 3, no. 3, pp. 304-309, 2011.