The proposed full adders for low power and high performance neural network training circuits has been implemented using Shannon decomposition based technique for sum and carry operation. The hardware includes multiplier circuit for product term and an adder circuit to perform summation. The proposed full adder is designed using tanner EDA tools and the resulting parameters such as 25.6% improvement in power dissipation and 20% improvement in transistor count from the simulated output when compared with MC IT based adder cell.
—MCIT, Shannon adder cell, power, area, propagation delay.
Cite: K. Nehru, A. Shanmugam, S. Deepa and R. Priyadarshini, "A Shannon Based Low Power Adder Cell for Neural Network Training," International Journal of Engineering and Technology
vol. 2, no. 3, pp. 258-262, 2010.